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M61113FP
Coil-less VIF/SIF
REJ03F0015-0100Z Rev.1.00 Aug.25.2003
Description
The M61113FP is a semiconductor integrated circuit built-in the PLL inter-carrier method VIF/SIF dedicated to NTSC. The circuit includes the VIF amplifier, image waveform detection, APC detection, IF/RF, AGC, VCO, AFT, LOCK DET, EQ, AF amplifier, limitter, FM waveform detector circuits, and acts as a small tuner.
Features
* * * * * Built-in VCO coil for intermediate frequency signal processing AFT adjustment is not required and flat temperature characteristics is realized Reference frequency of 3.58 MHz/4.00 MHz Image intermediate frequency US (47.75 MHz)/JP (58 .75 MHz) VIF/SIF mute function Coil-Less VIF/SIF
Recommended Operating Conditions
* Power-supply voltage range: 4.75 to 5.25 V * Recommended power-supply voltage: 5.0 V
Application
* TV, VCR
Pin Configuration
Video out Video in Vcc Video det ou APC VCO F/B (Defeat) SIF in (Delay Point) SIF out (US / JP SW) Audio out Audio Level Cont.
1 2 3 20 19 18
EQ AMP F/B IF AGC 2 IF AGC 1 VIF in 2 VIF in 1 GND RF AGC AFT Logic Vcc Ref Signal (3.58/4.00)
M61113FP
4 5 6 7 8 9 10
17 16 15 14 13 12 11
Rev.1.00, Aug.25.2003, page 1 of 16
AMP
AF AMP
Ref Signal (3.58/4.00) (3.58/4.00)
FM Det
11
Audio Level Cont. Level Cont. Audio out SIF out SIF out (US / JP SW) (US / JP SW) SIF in SIF in (Delay Point) (Delay Point)
Logic Vcc
12
LIM A MP
AFT
13
SIF A MP
A FT
RF A GC
RF AGC RF AGC
14
LPF
A PC
GND GND
15
7
8 6 5 4
9
10
VCO F/B (Defeat) VCO F/B (Defeat) APC APC Video det out
VIF A MP
VIF in 1 VIF in 1
16
VIF in 2
17
Video Det
Coil-less V CO
IF AGC 1 IF AGC 1 IF AGC 2
19
Vcc Vcc
IF AGC Det
3
Video in
EQ A MP
2
EQ AMP F/B
Video out
20 1
Rev.1.00, Aug.25.2003, page 2 of 16
18
Block Diagram
M61113FP
M61113FP
Absolute Maximum Ratings
(25C, unless otherwise noted)
Parameter Supply voltage Total power dissipation Operating temperature Storage temperature Symbol Vcc Pd Topr1 Tstg Ratings 6.0 969 -20 to 75 -40 to 150 Unit V mW C C
Temperature Characteristics (Maximum Ratings)
1200 969 Mounting in standard circuit board
Power Dissipation Pd [mW]
1000
800 582
600
400
200
0 0 25 50 75 100 Ambient Temperature Ta [C] 125 150
Recommended Operating Conditions
(Ta = 25C, unless otherwise noted)
Parameter Supply voltage Functional supply voltage range Reference Frequency GND Terminal # 3, 12 3, 12 11 15 Ratings 5.0 4.75 to 5.25 3.579545 GND Unit V V MHz --
Rev.1.00, Aug.25.2003, page 3 of 16
M61113FP
Pin Function
Pin No. 1 Pin Name Video out Function Video out terminal. Equivalent Circuit
3
1
1.4mA
2
Video in
This terminal is input the video signal from Pin4 "Video det out" by SIF trap. Input this terminal to DC of Video det signal is necessary for IF AGC function.
3
100
2
3 4
Vcc Video det out
Power supply terminal for VIF and SIF. Video detector output terminal. SIF trap and SIF BPF are connected to this terminal. It is necessary connecting external resistor for drive, because open emitter configuration.
3
3
4
5
APC
APC filter terminal.
3
3.4V 21K 21K 300 300
5
200A 20
6
VCO F/B
VCO Feedback terminal. The feedback control is to keep the internal VCO of the uniform free-running frequency. This terminal has dual function, connecting to gnd select mode with VIF/SIF defeat.
3
To Defeat SW
1K 20K 10K
6
Rev.1.00, Aug.25.2003, page 4 of 16
M61113FP
Pin Function (cont)
Pin No. 7 Pin Name SIF in (Delay Point) Function RF AGC Delay terminal. 4.5 MHz SIF signal "LIM IN" is input at this pin which has dual function. The RF AGC Delay Point is set up of DC component is FM signal. Equivalent Circuit
3
3.7V
7K 40
7
5.1K 40p
160A
23K 17.5K
20K
8
SIF out (US/JP SW)
SIF output terminal. FM signal which is converted to 4.5 MHz is output. This pin has dual function of being VIF VCO type selection terminal. Connect to GND with 1.5 k; JPN "58.75 MHz" No connect; USA "45.75 MHz"
3
600
3.8V
8
1.2mA
9
Audio out
Sound output terminal. De-emphasis is achieved by external components.
3
9
0.8mA
10
Audio Level Cont.
AF Bypass terminal. It is connected to one of the input of a differential amplifier, external capacitor provides AC filtering. When resistor is connected in series with capacitor, it is possible to lower the amplitude of the audio output. when audio output terminal is not use, please connect this terminal to GND. Reference signal input terminal. It is input external signal with sinewave. In case of 4 MHz mode, connect to GND with 4.7 k.
3
4.0V
11
Ref Signal (3.58/4.00)
11
1.3K 4.5K
4K
200A
12
Logic Vcc
Power supply terminal for Logic and Ref amp.
12
Rev.1.00, Aug.25.2003, page 5 of 16
M61113FP
Pin Function (cont)
Pin No. 13 Pin Name AFT Function AFT output terminal. Because of pulse-like signal output, Smoothing capacitor is connected externally. Equivalent Circuit
3
350K 50
13
350K
14
RF AGC
RF AGC output terminal. It is current drive type.
3
50
14
500A
15 16 17
GND VIF in 1 VIF in 2
Ground terminal for VIF and SIF. IF signal after SAW filter is input. It is balance-type input.
15
3
2.3V
16 17
2K
2K 14K
18
IF AGC 1
19
IF AGC 2
IF AGC filter terminal 1. External capacitor affects AGC speed. Where this terminal is grounded, the effect of VIF amp, becomes minimum gain. IF AGC filter terminal 2.
3
10K 2.5K 50
19 18
20
EQ AMP F/B
Equalizer feedback terminal. It is possible to change the AC response of the video signal by attaching L, C, R to this terminal.
3
2.2K 500
20
7K
Rev.1.00, Aug.25.2003, page 6 of 16
M61113FP
Electrical Characteristics
General (Unless otherwise specified: Ta = 25C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. 1 2 3 4 Parameter VIF/SIF Vcc current Logic Vcc Current VIF/SIF Vcc current@Defeat Ref. signal input level Symbol Icc1 Icc2 Icc3 Fref Test circuit 1 1 1 1 Test point Pin3 Pin12 Pin3 Pin12 Pin11 Input point -- -- -- Pin11 Input signal -- -- -- -- SW condition -- -- SW6=2 Limits Min 44 3.2 6.3 50 Typ 63 4.7 9.0 100 Max 82 6.1 12.0 600 Unit mA mA mA mVpp Note#
VIF Section 1 (Unless otherwise specified: Ta = 25C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Parameter Video out Sync Tip level Video S/N Video Out Freq. response Input sensitivity Max. IF input IF AGC Range IF AGC voltage @80 dBuV Capture range U Capture range L Inter modulation D/G D/P RF AGC High voltage RF AGC Low voltage RF AGC delay point Symbol Vodet Vsync VoS/N BW VinMIN VinMAX GR IFAGC CR-U CR-L IM DG DP RFagcH RFagcL RFDP Test circuit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Test point TP1 TP1 TP1 TP1 TP1 TP1 -- TP19 TP1 TP1 TP1 TP4 TP4 TP14 TP14 TP14 Input point Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 -- Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 SG6 SG7 SG7 SG8 SG9 SG9 SG10 SG11 SG12 SW7=3 SW7=3 SW7=3 Input signal SG1 SG2 SG2 SG3 SG4 SG5 SW10=2 SW condition Limits Min 0.95 1.20 48 6 -- 101 49 2.7 0.80 1.38 32 -- -- 4.4 0 82 Typ 1.20 1.45 50 7 45 105 60 3.0 1.00 1.75 38 3 3 4.7 0.3 85 Max 1.45 1.70 -- -- 52 -- -- 3.3 -- -- -- 5 5 5.0 0.6 88 Unit Vpp V dB MHz dBuV dBuV dB V MHz MHz dB % deg V V dBuV 9 6 7 8 1 2 3 4 5 Note#
Rev.1.00, Aug.25.2003, page 7 of 16
M61113FP VIF Section 2 (Unless otherwise specified: Ta = 25C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. 21 22 23 24 25 Parameter AFT sensitivity AFT High voltage AFT Low voltage AFT Mute voltage AFT Center voltage @US mode AFT Center voltage @JP mode Symbol AFTH AFTL AFTM VaftUS Test circuit 1 1 1 1 1 Test point TP13 TP13 TP13 TP13 TP13 Input point Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Pin16, 17 Input signal SG13 SG14 SG15 SG16 SG2 SW condition Limits Min 10 4.3 0 2.4 2.40 Typ 26 4.7 0.3 2.5 2.65 Max 40 5 0.7 2.6 2.90 Unit mV/ kHz V V V V Note# 10 10 10
26
VaftJP
1
TP13
SG17
SW8=2
2.60
2.87
3.15
V
SIF Section (Unless otherwise specified: Ta = 25C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. 27 28 29 30 31 Parameter AF output level AF output THD Audio S/N Limiting sensitivity SIF output level Symbol VoAF THDAF AF S/N LIM SIFG Test circuit 1 1 1 1 1 Test point TP9 TP9 TP9 TP9 TP8 Input point Pin7 Pin7 Pin7 Pin7 Pin7 Input signal SG18 SG18 SG19 SG20 SG21 SG19 SW condition SW7=2 SW7=2 SW7=2 SW19=2 SW7=2 SW19=2 SW7=2 Limits Min 400 -- 50 -- 90 Typ 700 0.4 55 50 96 Max 1000 0.9 -- 55 102 Unit mVrms % dB dBuV dBuV 11 12 Note#
VCO Section (Unless otherwise specified: Ta = 25C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. 32 Parameter VIF VCO freerun @US mode VIF VCO freerun @JP mode Symbol FvcofUS Test circuit 1 Test point TP13 Input point -- Input signal -- SW condition SW10=2 SW13,19=2 SW8,10=2 SW13,19=2 Limits Min -500 Typ 0 Max +500 Unit kHz Note# 13
33
FvcofJP
1
TP13
--
--
-500
0
+500
kHz
13
Rev.1.00, Aug.25.2003, page 8 of 16
M61113FP
Test Circuit
Ref. Sig nal
51
0.1 0.1u
IF Sig nal
5V
51
0.01 0.01u
0.01u
0.1u
0.1 0.1u
1
2 SW13
0.01u
1
2 SW11
0.22 0.22u
SW19 TP19 20 19 18
TP14
TP13
0.0 1u 1
17
16
15
14
13
33 33u
12
11
RF AGC V IF A MP A FT IF AGC Det EQ AMP V ideo Det Coil-less V CO APC LPF LIM A MP SIF AMP FM Det AF A MP A MP
1
2
3
4
5
6 TP6
7
US
8
7.5K
9
10 SW10 1 2
SW8
0.01 0.01u
0.47 200 0.47u
33 33u
SW6 1
0.1 0.1u
JP
1000p
0.01 0.01u
5V
240
SW7 TP8 1 3 2 TP9
TP1 15 15u
330
1K TP4
51
LIM IN Signal
Note; This test circuit is based on RENESAS board for evarution.
Rev.1.00, Aug.25.2003, page 9 of 16
1.0K
0.47 0.47u
2
4.7K
M61113FP
Input Signal
SG 1 2 3 4 5 6 7 8 Termination with 50 ohm f0 = 45.75 MHz Vi = 90 dBuV f0 = 45.75 MHz Vi = 90 dBuV f1 = 45.75 MHz Vi = 90 dBuV f2 = Freq. Variable Vi = 70 dBuV f0 = 45.75 MHz Vi = Variable f0 = 45.75 MHz Vi = Variable f0 = 45.75 MHz Vi = 80 dBuV f0 = Freq. Variable Vi = 90 dBuV f1 = 45.75 MHz Vi = 90 dBuV f2 = 42.17 MHz Vi = 80 dBuV f3 = 41.25 MHz Vi = 80 dBuV f0 = 45.75 MHz Sync Tip Level = 90 dBuV 87.5% TV modulation 10 step waveform f0 = 45.75 MHz Vi = 70 dBuV f0 = 45.75 MHz f0 = 45.75 MHz f0 = Freq. Variable f0 = 45.75-0.5 MHz f0 = 45.75+0.5 MHz f0 = 45.75+/-0.5 MHz f0 = 58.75 MHz f0 = 4.5 MHz f0 = 4.5 MHz f0 = 4.5 MHz f0 = 4.5 MHz Vi = 100 dBuV Vi = Variable Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = 90 dBuV Vi = Variable Vi = Variable fm = 20 kHz CW CW CW fm = 20 kHz fm = 20 kHz CW fm = 20 kHz CW CW CW AM = 77.8% Mixed signal AM = 77.8% AM = 16.0% AM = 77.8% Mixed signal
9 10 11 12 13 14 15 16 17 18 19 20 21
CW CW CW CW CW CW CW CW fm = 1 kHz +/- 25 kHz dev CW fm = 1 kHz +/- 25 kHz dev CW
Rev.1.00, Aug.25.2003, page 10 of 16
M61113FP
Mode Select
(Recommended Condition: Ta = 25C Vcc = 5.0 V)
IF Defeat select Un defeat Defeat US/JP select US JP Ref signal select 3.58 M 4.00 M SIF defeat select Un defeat Defeat 6 pin condition DC Open 0 to 0.5 V 8 pin condition None Pull down (1.0 k +/-10%) 11 pin condition None Pull down (4.7 k +/-10%) 10 pin condition DC Open 0 to 0.3 V Recommendation -- GND Recommendation No resistance 1 k to GND Recommendation No resistance 4.7 k to GND Recommendation -- GND
Rev.1.00, Aug.25.2003, page 11 of 16
M61113FP
Notes
Note 1 Video S/N: VoS/N Input SG2 to VIF IN (Pin 16, 17) and measure the video out (TP1) noise in r.m.s. through a 5 MHz (-3 dB) L.P.F..
S/N=20log
0.7 x Vodet (Vpp) NOISE (rms)
(dB)
Note 2 Video Band Width: BW * Measure the 1 MHz component level of Video output TP4 with a spectrum analyzer when SG3 (f2 = 44.75 MHz) is input to VIF IN (Pin 16, 17). * Reduce f2 and measure the value of (f1-f2) when the (f1-f2) component level reaches -3 dB from the 1 MHz component level as shown below.
TP4
-3dB
1MHz
Note 3 Input Sensitivity: VIN MIN
BW
(f1-f2)
Input SG4 (Vi = 90 dBu) to VIF IN (Pin 16, 17) and then gradually reduce Vi and measure the input level when the 20 kHz component of Video output TP1 reaches -3 dB from Vo det level. Note 4 Maximum Allowable Input: VIN MAX * Input SG5 (Vi = 90 dBu) to VIF IN (Pin 16, 17), and measure the level of the 20 kHz component of Video output (TP1). * Gradually increase the Vi of SG and measure the input level when the output reaches -3 dB. Note 5 AGC Control Range: GR
GR = VinMAX - VinMIN (dB)
Note 6 Capture Range: CR-U * Increase the frequency of SG7 until the VCO is out of locked-oscillation. * And decrease the frequency of SG7 and measure the frequency fU when the VCO is locked.
CR - U = fU - 45.75 (MHz)
Note 7 Capture Range: CR-L * Decrease the frequency of SG7 until the VCO is out of locked-oscillation. * And increase the frequency of SG7 and measure the frequency fL when the VCO is locked.
CR - L = 45.75 - fL (MHz)
Rev.1.00, Aug.25.2003, page 12 of 16
M61113FP Note 8 Inter Modulation: IM * Input SG8 to VIF IN (Pin 16, 17), and measure video output TP1 with an oscilloscope. * Adjust AGC filter voltage TP19 so that the minimum DC level of the output waveform is Vsync. * At that time, measure TP1 with a spectrum analyzer. The inter modulation is defined as a difference between 0.92 MHz and 3.58 MHz frequency components. Note 9 RF AGC Delay Point (TV Mode): RFDP * Input SG12 to VIF IN (Pin 16, 17) and gradually reduce level and then measure the input level when RF AGC output (TP14) reaches 1/2Vcc, as shown below. * At that time, the state of Pin 7 is DC open.
TP14 Voltage
RFagcH
1/2Vcc
RFagcL
RFDP
SG12 Level (dBV)
Note 10 AFT sensitivity: , Maximum AFT Voltage: AFTH, Minimum AFT Voltage: AFTL * Input SG13 to VIF IN (Pin 16, 17) and set the frequency of SG13 so that the voltage of AFT output TP13 is 3 volt. The frequency is named f(3). * Set the frequency of SG13 so that the AFT output voltage is 2 volt. This frequency is named f(2). * In the graph shown below, maximum and minimum DC voltage are AFTH and AFTL, respectively.
=
1000 f(2) - f(3)
(mV) (KHz)
(mV/kHz)
TP13 Voltage AFTH 3V 2V AFTL
f (3)
f (2)
f (MHz)
Rev.1.00, Aug.25.2003, page 13 of 16
M61113FP Note 11 Audio S/N: AF S/N Input SG19 to SIF IN (Pin 7), and measure the output noise level of Audio output (TP9) with FLAT-r.m.s.. This level is named Vn1.
AF S/N = 20log
VoAF1 (mVrms) Vn1 (mVrms)
(dB)
Note 12 Limiting Sensitivity: LIM * Input SG20 to LIM IN, and measure the 1 kHz component level of AF output TP9 with FLAT-r.m.s.. * Input SG21 to LIM IN, and measure the noise level of AF output TP9 with FLAT-r.m.s.. * The input limiting sensitivity is defined as the input level when the difference between each 1 kHz components of audio output (TP9) is 30 dB, as shown below.
TP9 (rms)
SG20 while TP9 is input
30 dB
SG21 while TP9 is input SIF IN
LIM
Note 13 VIF VCO Freerun Frequency: FvcofUS/FvcofJP
(dBV)
* Input 3.579545 MHz to Ref IN (Pin 11), and set up SW as shown following.
SW No. 20 8 10 11 13 19 US Mode Setting 3 1 2 1 2 2 Condition Add to 2.5 V No-Connecting R GND No-Connecting R No-Connecting C GND JP Mode Setting 3 2 2 1 2 2 Condition Add to 2.5 V Connecting 1 k GND No-Connecting R No-Connecting C GND
*VCO SW: US/JP #Fref SW
* Measure the frequency of output signal at AFT out (TP13) each when be selected US or JP by SW10. * Measured frequency's are defined FaftUS (US Mode), FaftJP (JP Mode). The VCO freerun frequency is calculated by following.
* US Mode FvcofUS = 52.915 (MHz) - 2 x FaftUS (MHz) - 45.75 (MHz) * JP Mode FvcofJP = 65.925 (MHz) - 2 x FaftJP (MHz) - 58.75 (MHz) [MHz] [MHz]
Rev.1.00, Aug.25.2003, page 14 of 16
M61113FP
Application
IF Sig nal Ref. Signal
SAW
0.01 0.22 0.01
4.7K 0.1 0.1 0.0 1
3.58 4.00
47 47u 20 19 18 17 16 15 14 13 12 11
RF AGC VIF A MP A FT IF A GC Det EQ AMP Video Det Coil-less V CO A PC LPF LIM A MP SIF A MP FM Det AF AMP AMP
1
2
3
4
5
6
7
US
8
9 7.5K
10
33
0.0 1
200 0.47
JP
1000p
0.1
5V 240 15 330
1.0K
D e feat
1K
N on-D efeat
* By pass capacitance for Logic Vcc (Pin12) should be mounted close hard by Logic GND (Pin15) * In order to mitigate the surroundings lump by the VIF input, the balanced connection from a SAW filter to the VIF input pin of 16, 17 recommends a putter which serves as a 1t coil by Tip C or the jumper.
Special components SAW:SAF45MA210Z TRP:TPSRA4M50B00 BPF:SFSH4.5MEB2
Rev.1.00, Aug.25.2003, page 15 of 16
0.01
0.47
M61113FP
20P2F-A
MMP
JEDEC Code -- e b2
11
Plastic 20pin 255mil SSOP
Weight(g) -- Lead Material Cu Alloy
EIAJ Package Code SSOP20-P-255-0.65
20
Package Dimensions
I2
HE
E
L1
L
Rev.1.00, Aug.25.2003, page 16 of 16
F Recommended Mount Pad Symbol
1 10
A
G
D
A2
b
A1
e x
M
y
c
A A1 A2 b c D E e HE L L1 z Z1 x y Detail F b2 e1 I2
z Detail F
Z1
e1
Dimension in Millimeters Min Nom Max 1.45 -- -- 0 0.1 0.2 -- -- 1.15 0.32 0.17 0.22 0.13 0.15 0.2 6.6 6.4 6.5 4.3 4.5 4.4 0.65 -- -- 6.2 6.4 6.6 0.3 0.5 0.7 1.0 -- -- -- 0.325 -- -- -- 0.475 -- -- 0.13 -- -- 0.1 -- 0 10 -- 0.35 -- -- 5.8 -- 1.0 -- --
Sales Strategic Planning Div.
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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http://www.renesas.com
(c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
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